1. Field of the Invention
The present invention relates to a test assist circuit for a semiconductor device. More specifically, it relates to a test assist circuit for a semiconductor device, which is contained in a semiconductor device having a memory circuit for storing multiple-bit data and a logic circuit, for independently testing the memory circuit.
2. Description of the Prior Art
A well-known method of testing a memory assembled in a semiconductor device is disclosed in "Advanced Testing Techniques for Structured ASIC Products" reported by Rick Rasmussen, Yen Chang and Fred White, IEEE 1986, Custom Integrated Circuits Conference. In this method, registers are provided in correspondence to write data, address signals and read data respectively for testing a RAM contained in the semiconductor device, thereby to perform a test for accessing the RAM with a small number of external pins.
FIGS. 1 and 2 are illustrative of a conventional test assist circuit for testing a memory circuit. Referring to FIG. 1, a semiconductor device 1 is provided with a logic circuit 2, a memory circuit 3, an address decoder 4, an input data register 5 and an output data register 6. As shown in FIG. 2, the logic circuit 2 includes a CPU 201, an output data register 202, an address register 203 and an input data register 204, such that the CPU 201 outputs internal data through the output data register 202 and an internal address signal through the address register 203. The input data register 204 is adapted to supply data read from the memory circuit 3 to the CPU 201. The memory circuit 3 has memory of 3 bits by 8 words, for example.
The semiconductor device 1 is further provided with an address input terminal 7, a data input terminal 8, a data output terminal 9, data shift clock terminals 20 and 22, a latch clock terminal 21 and an input/output data latch clock terminal 23. The address input terminal 7 receives a bit-serial address signal of three bits, for example. The data input terminal 8 is externally supplied with bit-serial input data of three bits, for example. The data output terminal 9 is adapted to output bit-serial data to the exterior. The data shift clock terminal 20 is supplied with a data shift clock signal for shifting the address signal received in the address input terminal 7 and storing the same in the address decoder 4 as well as shifting the input data received through the data input terminal 8 and storing the same in the input data register 5.
The latch clock terminal 21 is supplied with a latch clock signal for supplying the address signal stored in the address decoder 4 to the memory circuit 3. The data shift clock terminal 22 receives a data shift clock signal for sequentially shifting data of the output data register 6, which stores output from the memory circuit 3, to the data output terminal 9. The input/output data latch clock terminal 23 is supplied with an input/output data latch clock signal for writing the input data stored in the input data register 5 into the memory circuit 3 and storing the data read from the memory circuit 3 in the output data register 6.
The internal address signal outputted from the address register 203 of the logic circuit 2 and the external address signal received in the address input terminal 7 are switched by an address input selector 14a, to be supplied to the address decoder 4. The internal data outputted from the output data register 202 of the logic circuit 2 and the external input data received in the data input terminal 8 are switched by input data selector 14b to be supplied to the input data register 5. Further, the data outputted from the output data register 6 is switched by an output data selector 14c, to be supplied to either the data output terminal 9 or the input data register 204 of the logic circuit 2.
With reference to FIGS. 1 and 2, description is now made on operation for writing/reading data in/from the memory circuit 3. In order to write data in the memory circuit 3 through operation of the logic circuit 2, the address input selector 14a, the input data selector 14b and the output data selector 14c are switched toward the logic circuit 2 respectively. The address register 203 of the logic circuit 2 outputs an internal address signal, which in turn is supplied to the address decoder 4 through the address input selector 14a. This address signal is formed by three bits, for example, to be capable of addressing of 2.sup.3 =8 combinations. Vertical memory elements of the memory circuit 3 are addressed by this address signal.
The output data register 202 of the logic circuit 2 outputs three-bit internal data in a bit-serial manner, which internal data is supplied to the input data register 5 through the input data selector 14b. Then an input/output data latch clock signal is supplied to the input/output data latch clock terminal 23 and a data shift clock signal is supplied to the data shift clock terminal 20, whereby the input/output data register 5 stores the internal data so that the three-bit internal data is outputted to the memory circuit 3 in a bit-serial manner, to be written in the addressed memory elements.
In order to read data from the memory circuit 3, the address decoder 4 addresses arbitrary memory elements similarly to the case of write operation, so that data is read from the memory elements to be supplied to the output data register 6. The output data register 6 latches the data read from the memory elements on the basis of an input data latch clock signal received in the input/output data latch clock terminal 23. Then a data shift clock signal is supplied to the data shift clock terminal 22, so that the output data register 6 sequentially reads the latched data in a bit-serial manner. The data is supplied to the input data register 204 of the logic circuit 2 through the output data selector 14c.
Description is now made on test operation for the memory circuit 3. In order to test the memory circuit 3, the address input selector 14a is switched toward the address input terminal 7 and the input data selector 14b is switched toward the data input terminal 8, while the output data selector 14c is switched toward the data output terminal 9. An address signal is externally inputted in the address input terminal 7, to be supplied to the address decoder 4 through the address input selector 14a. Input data is externally supplied to the data input terminal 8, to be supplied to the input data register 5 through the input data selector 14b. A data shift clock signal is supplied to the data shift clock terminal 20, so that the address signal is stored in the address decoder 4 and the input data is stored in the input data register 5 on the basis of the data shift clock signal. The address decoder 4 addresses arbitrary memory elements, so that the input data, being stored in the input data register 5, is stored in the addressed memory elements.
Then, the address decoder 4 addresses arbitrary memory elements of the memory circuit 3 similarly to the case of write operation, so that data is read from the memory elements to be supplied to the output data register 6. An input/output data latch clock signal is supplied to the output data register 6, so that the data read from the memory elements is latched by the output data register 6. Then a data shift clock signal is supplied to the output data register 6, so that bit-serial data is outputted from the output data register 6, to be outputted to the data output terminal 9 through the output data selector 14c. Thus, a test can be made as to whether or not the data is correctly written and read by judging whether or not the outputted data is in coincidence with the data supplied to the data input terminal 8.
In the conventional semiconductor device 1 as hereinabove described, the address input selector 14a, the input data selector 14b and the output data selector 14c are switched toward the terminals 7, 8 and 9 respectively while addressing the memory circuit 3, thereby to test whether or not input data is normally written/read in/from respective memory elements. However, if the data is not normally written in or read from the memory circuit 3, it is impossible to judge whether the memory circuit 3 itself is in failure or a test assist circuit 30, being formed by the address decoder 4, the input data register 5 and the output data register 6, is in failure. Even if the memory circuit 3 is normal, correct data cannot be read in the memory circuit 3 when a single-bit area in the input data register 5 is in failure, as a matter of course. Further, if the address decoder 4 is in failure, the target memory elements cannot be addressed and hence the data cannot be correctly written in the same. In the conventional test assist circuit 30, therefore, a great deal of effort and time are required to analyze the cause of abnormal data reading or writing.